Dear Embedded Community,
We have a Haswell based processor design. It has two DIMMs,
one connected to each of the two DDR controllers. The "A"
DIMM appears to work. The "B" DIMM gets occasional errors
and the processor will often crash during booting Linux or
some time afterwards.
We are seeing some differences between the "A" and "B" DIMM
signals. We have been triggering on ODT. We believe that when
ODT is high, this should mean that the processor is driving DQS
and data towards the DIMM.
In the attached traces, the pink signal is ODT and the yellow and
blue signals are DQSxP/N.
In the attached trace for DIMM A DQS7, APR2i_A_DQS7_ODT.tif,
during ODT we get what we would expect: ODT asserted, followed
by eight clock edges then ODT deasserted.
But in the attached trace for B DQS2, APR2i_B_DQS2_ODT.tif,
during ODT we get an initial bad clock transition. Followed
by some O.K. clocks, then clock seven seems to be just plain
missing. I particularly don't understand the missing clock.
The DIMM "B" trace lengths follow the requirements in the
Haswell Desktop and Denlow-WS Platform Design Guide, 486711
Is there any explanation that you can give us for the very
odd behaviour of the clocks on the "B" DIMM?
We can send the Allegro .brd layout file if this would be useful.
Does Intel offer a layout examination service? This would be very
helpful. We have had the schematics looked at by Intel in the past.
Thanks, Paul.