Dear All,
We have a board with two I210 parts on it.
The I210 communicates with a PHY on a daughter card.
We have two different types of daughter card. One has
a Marvell 88E1111 device and the other has a Marvell 88E1512
part on it.
I turned on the debugging messages in the Intel driver software.
With the 88E1512 board, I see a lot of routines being called,
but the PHY doesn't get set up correctly. On power up the
RJ45 side of the PHY gets linkup to a switch, but not after
the driver code runs. So, my question is has this particular
combination of I210 and PHY been tested recently? It
obviously requires a lot of work to test every release of
software with every possible hardware permutation.
With the 88E1111 we have problems with getting occasional MDIO errors
when the I210 is doing MDIO reads. On reading the code, the
"MDI Error" message is triggered by the MDI_ERR bit being
set in the I210's MDIC register (0x20).
On page 377 of the I210 manual, there is the statement:
This bit is set to 1b by hardware when it fails to complete an MDI read.
Software should make sure this bit is clear (0b) before issuing an MDI read
or write command.
My question is what triggers the setting of this bit? The MDIO
protocol has no handshaking with the MDIO slave. If there is
no slave at all, the MDIO master will just drive the read pattern,
followed by the PHY address and register address. After that the
pull-up will pull the MDIO data line high, and all ones will be read.
How do you get an error?
Thanks, Paul.
