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How to connect four xl710 to one x557
Hello, we want configuration is shown in Figure. Connect the xl710 to four different CPU and connect to a 4port x557(X557-AT4) we could't find this contents in datasheet or reference schematics. Is it...
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CPLD consumption
Hi, I'm using a 5M570ZT144C5N CPLD to light 100 LEDs. Each LED is connected in a IO pin. Each LED need 10mA. That is to say each pin pass 10mA.If all the LEDs are lighted at the same time, I have more...
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Curtiss-Wright and Green Hills Software Demonstrate INTEGRITY-178 tuMP...
Intel® Quad-Core Xeon® processor-based VPX3-1220 RTCA/DO-254 safety-certifiable COTS SBC supports Green Hills Software RTCA/DO-178B Level A certifiable multi-core RTOS ASHBURN, Va. – August 14, 2018...
View ArticleMTBF for Intel CPUs
Hi, Would anybody help me to find the MTBF or FIT reliability information for the following Intel parts? FH8065301487717 SR1X6 CPULH8066803102601 SR33P CPU10M02SCU169I7G FPGA Thank you very much! John
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Where is the Intel/Altera FPGA section of the forums?
Hi all. Is there an area of the forum on the subject of Intel Altera FPGAs, and all things FPGA related? I am used to the layout of the Altera forum boards and i seem to be having trouble navigating...
View ArticleE3930 PCIe memory access issues
Hi, the tested E3930 SoC (microcode: sig=0x506c9, pf=0x1, revision=0x2c) has issues accessing the 32-bit non-prefetchable memory resource of Xilinx PCIe Endpoint (Vendor 10EE Device 0007). Within each...
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Application/algorithm efficiency - MIPS versus DMIPS
Dear all, We are trying to have a rough comparison measure of efficiency of a set of algorithms running across different CPU architectures and trying to understand how we can express it in an...
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Live mobile video & IoT sensor monitoring for First Responders
FirstNet certified, enabling Fire, Police & Paramedics, LiveCast’s solutions are used for in variety of mission critical situations every day. Wireless, mobile video solutions are transforming the...
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Broadwell-DE No MDC/MDIO
Hi, Problem: No MDC/MDIO signalCPU: Broadwell-DE SoC, 4Core/8T10G BASE –T PHY: Intel, X557-ATFlash Image:1. BDXDE_KR_BACKPLANE_LED_LO_NO_MNG_1.13v02_800006D1.bin2....
View ArticleCreate Online push notification for smartphones to monitor Wireless Contact...
Hello, I want to create the point to point switching technique using the wireless contact closure transmitter Wireless Contact Closure Remote SPDT Relay Controller 2-Channel 1-Way - store.ncd.io and...
View ArticleConfigure both DDI ports as DP in ATOM E3826
I'm want to know that can we configure both DDI ports of Intel ATOM E3826 as Display port simultaneously?Is there limitation to this configuration? As mentioned datasheet both can be configured as eDP...
View Article关于E3825的一些问题
我查询了此芯片的芯片资料，发现此芯片的集成度非常高，那此芯片的总线信号是直接接出就可正常使用，还是需要加一些什么转换芯片。跟此芯片配套的南桥和北桥芯片是什么？
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Intel Atom® E3900 available on sale
I can not find this processor on sale.But I see on sale a lot of modules with this processor.To start my project, I need to buy it.Who will tell the distributor, or is there another ability? I would be...
View Articleeeupdate for ARM64
Dear Intel Team, We already check Intel Network Connection Tools, but tools didn’t support Linux Arm64.Could you provide us eeupdate ARM tool to update i210 NVM for our ARM64 SoC.Please send to:...
View ArticleChipset Number used in Intel Atom E3815 processor type
Hi Team, Please help in letting us know the Chipset number used in Atom E3815 processor. We are using the Intel® Chipset Device Software (INF Update Utility) Version:10.1.1.42 in our devcie that uses...
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Xeon D-1539 integrated 10Gb phy power
We have a Xeon 1539 10Gb KR connected via backplane to a Kintex Ultrascale (KU115) FPGA and are having data quality issues when sending from the Xeon to the FPGA. There are a lot of bit errors when...
View ArticleE3930集成显卡只能运行direct9 , 无法运行direct10 & direct 11
型号：INTEL(R) ATOM (TM) E3930 BIOS将E3930 CPU 进行限频到1.3GHz运行，生产100pcs 主板，pc doctor 进行测试，其中一台主板，direct9 测试pass, direct 10 & direct 11 测试fail, 显示direct 10 & direct 11无法运行. 其他99台测试direct 9 & 10...
View ArticleSIO_SPI_1 for UART configuration
Based on Apollo lake SOC which is in MRB board, we want to configure SIO_SPI_1 as one UART port according to the document #562447 (looks SPI_1 can be set as LPSS_UART3).however from Intel document...
View ArticleTrying PLEVT at cannon lake platform
Hello all, I trying PLEVT (Ver 1_13_1) at cannon lake platform.However I can not indicate test menus.Does know that PLEVT supposed to cannon lake platform? Thanks a lot.Mao
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Case Study: AWACS Network Upgrade using Modified COTS Helps Shorten Delivery
For the majority of operational airborne early warning and control aircraft (AEW&C) over 20 years old, on-board radar and networking systems are based on outdated technology that need to be...
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