Hello,
we want configuration is shown in Figure. Connect the xl710 to four different CPU and connect to a 4port x557(X557-AT4)
we could't find this contents in datasheet or reference schematics.
Is it possible to connect 4 xl710 to one x557 as shown ???
Thanks..
Hi,
I'm using a 5M570ZT144C5N CPLD to light 100 LEDs. Each LED is connected in a IO pin. Each LED need 10mA. That is to say each pin pass 10mA.
If all the LEDs are lighted at the same time, I have more than 1A in all the IO pin. I think it's too much.
So can I connec directly the 100 pin to light the 100 LEDS?
ASHBURN, Va. – August 14, 2018 --Curtiss-Wright’s Defense Solutions division today announced that Green Hills Software’s field-proven INTEGRITY-178 tuMP safety- and security-critical multi-core real-time operating system (RTOS) was recently demonstrated on the Curtiss-Wright VPX3-1220 module, an RTCA/DO-254 Design Assurance Level (DAL) C safety-certifiable 3U OpenVPX™ single board computer (SBC). The rugged module features the Intel® Xeon® E3 processor (formerly known as “Kaby Lake”) and enables avionics system designers to rapidly integrate Commercial Off-the-Shelf (COTS) system solutions based on the INTEGRITY-178 tuMP RTOS. INTEGRITY-178 tuMP is the industry’s only multi-core RTOS that enables users to utilize all available compute power from the Xeon E3 processor’s quad cores, including its virtual cores, all based on deterministic, user-defined core and scheduling assignments. With its embedded Intel® Core™ technology design, the VPX3-1220 SBC brings unprecedented computing power to certifiable mission computing and critical airborne applications.
The VPX3-1220’s low-power mobile Xeon E3 processor, which is ideal for airborne applications, delivers high-performance, quad-core x86 processing with integrated graphics at 50% of typical power levels compared to previous Intel processor solutions. Paired with the INTEGRITY-178 tuMP operating system (OS), the SBC provides a compelling combination of hardware and software for system integrators that require optimal processing power and industry-leading size, weight and power (SWaP) benefits for their multi-core critical systems.
“Support for Green Hills’ INTEGRITY-178 tuMP multi-core RTOS on the VPX3-1220 SBC demonstrates Curtiss-Wright’s dedication to raising the performance bar for safety-certifiable avionics, while simplifying the complex DO-254/DO-178 safety certification process for our embedded avionics customers,” said Lynn Bamford, Senior Vice President and General Manager, Curtiss-Wright Defense Solutions division. “Our ongoing collaboration with trusted operating system vendors, such as Green Hills, enables us to deliver complete COTS-based, safety-certifiable hardware and software solutions to the embedded defense and aerospace market.”
For programs with DO-254 DAL A or DAL B requirements, or system designers seeking a Power Architecture®-based SBC, Curtiss-Wright offers the NXP® QorIQ® T2080-based VPX3-152, a DO-254 DAL A safety-certifiable 3U OpenVPX SBC that also supports INTEGRITY-178 tuMP. In addition, earlier this year, Curtiss-Wright announced support for the INTEGRITY-178 tuMP RTOS on its T2080 SOC-based VPX3-133 3U OpenVPX SBC. The VPX3-133, combined with INTEGRITY-178 tuMP, is ideal for rugged deployed applications that do not require DO-254 safety-certifiable hardware.
The VPX3-1220 and VPX3-152 are compatible with Curtiss-Wright’s entire safety-certifiable module portfolio, including the VPX3-717 and VPX3-719 safety-certifiable OpenVPX graphics processors, and the VPX3-611 safety-certifiable MIL-STD-1553B and ARINC 429 I/O Module.
About the VPX3-1220
Designed with RTCA/DO-254 in mind from the beginning of the development cycle, the VPX3-1220 is offered with an RTCA/DO-254 DAL C data artifact package to speed and ease the safety certification process. It is the industry’s first multi-core Intel Xeon-based SBC designed to meet DO-254 DAL C for use on safety-critical military and civil aerospace platforms. Delivering the highest possible processing performance while consuming low power, the VPX3-1220 is ideal for mission computing applications in SWaP-constrained aerospace and defense systems. Use of this SBC accelerates and simplifies the integration of Intel Xeon-class processing into demanding deployed applications, such as mission computing and image and display processing.
Leveraging the strong partnership between Curtiss-Wright and Green Hills Software, INTEGRITY-178 tuMP on the Xeon E3 processor-based VPX3-1220 provides avionics system integrators with support for the first true multi-core OS to conform to any version of the FACE Technical Standard. The RTOS conforms to both the FACE Safety Base and Security Profiles for the C, C++ and Ada programming languages. The INTEGRITY-178 tuMP multi-core OS meets all of the requirements defined in the current standard for ARINC-653, Supplement 4, which requires multi-core operation per Section 2 of the Supplement 4 standard, and defines support for “Multiple processes within a partition scheduled to execute concurrently on different processor cores,” and support for “Multiple partitions scheduled to execute concurrently on different processor cores.”
The INTEGRITY-178 tuMP RTOS has successfully met the DO-178 DAL A certification objectives multiple times across several different multi-core SOC architectures, with each SOC having a different core design. It also satisfies the CAST-32A Position Paper for multi-core interference mitigation. The combination of INTEGRITY-178 tuMP’s time-partitioned AMP and SMP capabilities, with support for multi-core interference mitigation, provides the industry’s best core utilization and overall SOC throughput. This enables the VPX3-1220 to deliver unmatched SWaP reduction.
The VPX3-1220 SBC is available now for both air-cooled and conduction-cooled environments.
Curtiss-Wright Corporation is a global innovative company that delivers highly engineered, critical function products and services to the commercial, industrial, defense and energy markets. Building on the heritage of Glenn Curtiss and the Wright brothers, Curtiss-Wright has a long tradition of providing reliable solutions through trusted customer relationships. The company employs approximately 8,600 people worldwide. For more information, visit www.curtisswright.com.
###
Hi,
Would anybody help me to find the MTBF or FIT reliability information for the following Intel parts?
| FH8065301487717 SR1X6 CPU |
| LH8066803102601 SR33P CPU |
| 10M02SCU169I7G FPGA |
Thank you very much!
John
Hi all. Is there an area of the forum on the subject of Intel Altera FPGAs, and all things FPGA related?
I am used to the layout of the Altera forum boards and i seem to be having trouble navigating the Intel website, so i may be missing something as i am new to this site.
Thanks.
Hi,
the tested E3930 SoC (microcode: sig=0x506c9, pf=0x1, revision=0x2c) has issues accessing the 32-bit non-prefetchable memory resource of Xilinx PCIe Endpoint (Vendor 10EE Device 0007). Within each block of 80-84 bytes only four starting dwords get read correctly, the next dword is the product of dword address, remaining data is zeroed. While the real memory contents are random non-zero data.
The problem appears only on E3930 (in a form of Qseven module), while the same PCIe endpoint works fine with E3845, E3815, x5-E8000. It's also reproducible with Linux (4.8, 4.14) as well as with EFI Shell, changing the PCI/PCIe configuration doesn't appear to help. No errors reported by endpoint/root port.
EFI Shell dump (zeroed data returned is incorrect):
Memory Address 0000000091200000 256 Bytes
91200000: D7 16 2A 88 05 24 64 21-64 80 01 03 00 4C 00 04 *..*..$d!d....L..*
91200010: 00 00 25 04 00 00 00 00-00 00 00 00 00 00 00 00 *..%.............*
91200020: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200030: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200040: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200050: 00 00 00 00 06 00 20 85-00 00 35 16 09 80 1E 21 *...... ...5....!*
91200060: A7 88 46 20 00 00 31 19-00 00 00 00 00 00 00 00 *..F ..1.........*
91200070: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200080: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200090: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
912000A0: 00 00 00 00 00 00 00 00-E2 90 90 0A 00 00 21 2B *..............!+*
912000B0: 00 00 25 2C 00 28 AD 01-00 00 25 2E 00 00 00 00 *..%,.(....%.....*
912000C0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
912000D0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
912000E0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
912000F0: 00 00 00 00 00 00 00 00-00 00 00 00 C3 B0 0C 71 *...............q*
91200100: 28 42 84 42 0A 20 00 87-08 81 49 00 20 55 54 81 *(B.B. ....I. UT.*
91200110: 00 00 25 44 00 00 00 00-00 00 00 00 00 00 00 00 *..%D............*
91200120: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200130: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200140: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200150: 00 00 00 00 20 8A 9C 81-00 00 35 56 08 21 C9 57 *.... .....5V.!.W*
91200160: 00 08 88 81 00 00 31 59-00 00 00 00 00 00 00 00 *......1Y........*
91200170: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200180: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200190: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
912001A0: 00 00 00 00 00 00 00 00-A5 10 00 18 00 00 21 6B *..............!k*
912001B0: 00 00 25 6C 01 04 C4 40-00 00 25 6E 00 00 00 00 *..%l...@..%n....*
912001C0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
912001D0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
912001E0: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
912001F0: 00 00 00 00 00 00 00 00-00 00 00 00 2C 40 42 10 *............,@B.*
91200200: 00 12 84 0D 10 26 0C 01-79 C0 00 12 4A E0 8E 12 *.....&..y...J...*
91200210: 00 00 35 04 00 00 00 00-00 00 00 00 00 00 00 00 *..5.............*
91200220: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200230: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200240: 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 *................*
91200250: 00 00 00 00 81 21 *.....!*
Dear all,
We are trying to have a rough comparison measure of efficiency of a set of algorithms running across different CPU architectures and trying to understand how we can express it in an architecture independent ways. We could measure the MIPS from Intel's vTune or similar tool for the algorithms running on Intel's CPU. However, we can not use the MIPS to compare the same figure for the same algorithms to that of ARM core. I am thinking of figuring out a rough way to convert MIPS to DMIPS and use DMIPS as a way to compare the efficiency of the algorithm across different CPU cores. I do understand the host of limitations of such a measure (wait states, Cache etc.). Now, (1) do you think it is a reasonable method to do so or is there any better way to do this ? (2) how to convert MIPS to approximate DMIPS for different CPU cores ? Many thanks for your support !
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Hi,
Problem: No MDC/MDIO signal
CPU: Broadwell-DE SoC, 4Core/8T
10G BASE –T PHY: Intel, X557-AT
Flash Image:
1. BDXDE_KR_BACKPLANE_LED_LO_NO_MNG_1.13v02_800006D1.bin
2. BDXDE_10GBASET_NO_MNG_1.13v02_800006B7.bin
===========Eth Info==================
root@genericx86-64:/dni# ethtool -i eth1
driver: ixgbe
version: 5.0.0-k
firmware-version: 0x800006a8
expansion-rom-version:
bus-info: 0000:04:00.0
supports-statistics: yes
supports-test: yes
supports-eeprom-access: yes
supports-register-dump: yes
supports-priv-flags: yes
===========Eth Info End==================
04:00.0 Ethernet controller: Intel Corporation Ethernet Connection X552 10 GbE Backplane
04:00.1 Ethernet controller: Intel Corporation Ethernet Connection X552 10 GbE Backplane
Description:
We try to do MDI single r/w through MSCA(0x0000425c) and MSRWD(0x00004260).
The rule and steps is shown below
04:00.0 [Base address] + [offset] [32 bits] [value]
devmem 0x383fff400000+0x0000425c 32 0x501dc501 //Address cycle PHYAD = 0x00
devmem 0x383fff400000+0x00004260 32 0x00002001 //Test Mode 1
devmem 0x383fff400000+0x0000425c 32 0x541dc501 //Write operation
Is it correct?
We also try to use the tool of "lanconf64e" doing "IEEE Tests", but we still cannot got MDC/MDIO signal.
Then, we upgrade flash to BDXDE_10GBASET_NO_MNG_1.13v02_800006B7.bin.
However, the situation is the same.
Another question is when we use BDXDE_10GBASET_NO_MNG_1.13v02_800006B7.bin, the eth cannot link up.
If we change the image to XXX_BACKPLANE..., it can link up in 1G. But, 10G doesn't work...
Why we can't get MDC/MDIO signal?
In backplane mode, why X557 only link up in 1G?
Could you give us some suggestions?
Thanks
Hello, I want to create the point to point switching technique using the wireless contact closure transmitter Wireless Contact Closure Remote SPDT Relay Controller 2-Channel 1-Way - store.ncd.io and send the notifications to smartphones via the internet, the wireless receiver is also communicating at same time with Arduino which is further using ESP32 to connect via online servers but looking for suggestion to create push notification for smartphones to make this kind of process work, leads on this will be much appreciated.
I'm want to know that can we configure both DDI ports of Intel ATOM E3826 as Display port simultaneously?
Is there limitation to this configuration?
As mentioned datasheet both can be configured as eDP at same time. Does this applies to HDMI and DP also?
我查询了此芯片的芯片资料，发现此芯片的集成度非常高，那此芯片的总线信号是直接接出就可正常使用，还是需要加一些什么转换芯片。跟此芯片配套的南桥和北桥芯片是什么？
I can not find this processor on sale.
But I see on sale a lot of modules with this processor.
To start my project, I need to buy it.
Who will tell the distributor, or is there another ability? I would be helped at least by samples.
Dear Intel Team,
We already check Intel Network Connection Tools, but tools didn’t support Linux Arm64.
Could you provide us eeupdate ARM tool to update i210 NVM for our ARM64 SoC.
Please send to: via.lee@adlinktech.com
Hi Team,
Please help in letting us know the Chipset number used in Atom E3815 processor.
We are using the Intel® Chipset Device Software (INF Update Utility) Version:10.1.1.42 in our devcie that uses Intel Atom processor E3815.
But we are not able to identify the chipset number used in Intel Atom E3815 processor.
Please guide help us
We have a Xeon 1539 10Gb KR connected via backplane to a Kintex Ultrascale (KU115) FPGA and are having data quality issues when sending from the Xeon to the FPGA. There are a lot of bit errors when transmitting known patters via UDP.
FEC is off; auto-neg and link training are on although there is some question as to whether the FPGA performs any analysis of the training data and just indicates the link is OK.
We have eye diagrams from the FPGA receive side that indicate a poor quality connection.
Are there any registers where we can tweak the power level (or other parameters) on the Xeon transmit side? I ask here because Xeon D1500 data sheet seems to be missing the integrated PHY registers(?). (Section 3.8.1 links to appendix B and appendix B(B.5) links to section 3.8.1)
型号：INTEL(R) ATOM (TM) E3930
BIOS将E3930 CPU 进行限频到1.3GHz运行，生产100pcs 主板，pc doctor 进行测试，其中一台主板，direct9 测试pass, direct 10 & direct 11 测试fail, 显示direct 10 & direct 11无法运行. 其他99台测试direct 9 & 10 & 11 都是pass的. 这台问题主板将限频设置关闭，重新测试PC doctor , director 9 & 10 & 11测试pass, 重新打开限频，再次测试，direct9 测试pass
如上问题板有更新如下VGA driver ,问题没有任何改善
原显卡驱动版本：22.20.16.4836
更新显卡驱动版本：22.20.16.4729
Based on Apollo lake SOC which is in MRB board, we want to configure SIO_SPI_1 as one UART port according to the document #562447 (looks SPI_1 can be set as LPSS_UART3).
however from Intel document #557555 EDS file: "the SPI functionality of SIO_SPI_1 and SIO_SPI_2 is not POR and these signals can be used as GPIOs ONLY."
Can Intel clarify which one statement is correct ?
thanks.
Hello all,
I trying PLEVT (Ver 1_13_1) at cannon lake platform.
However I can not indicate test menus.
Does know that PLEVT supposed to cannon lake platform?
Thanks a lot.
Mao
For the majority of operational airborne early warning and control aircraft (AEW&C) over 20 years old, on-board radar and networking systems are based on outdated technology that need to be upgraded to be effective in today’s airborne defense engagements. When one such aircraft fleet was undergoing an upgrade of the on-board AEW&C network, they contacted Curtiss-Wright to find a cost effective yet rugged, quick turnaround solution for multiple processing and communications subsystems.
To withstand the harsh environmental conditions on-board the fixed wing aircraft, the equipment needed to meet DO-160 environmental, EMI, and power hold-up requirements. Electronics also had to be export controlled as commercial items and be available in time to meet the customer’s tight integration schedule. Additionally, they needed to ensure that the processor architectures used could handle single event upsets (from space radiation) by incorporating Error Correcting Code (ECC) memory and non-volatile removable Flash disks (to support sanitize procedures). Due to the sensitive nature of the data the system would handle, the integrator was interested in Intel-based solutions coupled with secure Cisco routing technology that had gone through FIPS 140 and Common Criteria evaluations, as provided by the Cisco 5915 Embedded Services Router.
To keep program risk, costs and total system footprint down, the customer’s network architecture upgrade included four Small Form Factor (SFF) systems from Curtiss-Wright, ten in total on each aircraft, with redundancies included. To learn more about the MCOTS Systems Curtiss-Wright designed based on Intel Xeon processors and Cisco-based Router/Switches, download the AWACS Network Upgrade Case Study.
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