The ixgbe driver references these registers for configuring the KR Ethernet.  Where can I find documentation for them?  Doesn't appear to be in D-1500 family Vol 4 datasheet.

From ixgbe_type.h:

#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)

#define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200)

#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)

#define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)

#define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238)

#define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248)

#define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918)

#define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C)

#define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0)

#define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C)

#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)

#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)

#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)

#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)

#define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054)

#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)

#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)

Hi,

I’m working on a design with three i210 AT network controllers, all connected to the same CPU. To avoid interference, I would prefer to connect all three network controller to the same clock source. My plan ist o use an oscillator as clock source and a fan out buffer to distribute the clock to the three controllers.

Do you have any experience with such a design and can you propose any components? Also some questions stay not answered after working my way through the various documents.

In the Intel® Ethernet Controller i210 Datasheet in section 11.6.5.2 it is suggested to use a capacitive voltage divider with a capacitance of C1 = 51 pF when using a 3.3 V clock signal. Also in section 12.4 it is mentioned that the input capacitance is about 20 pF. So the circuit would look like this.

If I calculate equivalent capacitance of all three capacitors, I get a value of 29 pF. Most fan out buffers are only able to drive a load up to 15 pF. Is there a way to use smaller capacitors or do you know any buffers that have a high enough performance?

Even if I can reduce the equivalent capacitance, the fan out buffers I found have only 8 to 12 mA output current. So the rise or fall time is even in best scenario about 6 ns, which seems suspiciously long for a period of 40 ns (25 MHz!). Can you confirm, that such a long rise time would be no problem?

Thank you very much for helping me with this problem.

Best regards

Sebastian

Embedded systems are normally resident in machines that are expected to run continuously for years without errors. Therefore the software and Firmware is usually developed and tested very rigorously and meticulously. Embedded systems generally avoid mechanical moving parts such as Disk drives, switches or buttons because these are unreliable compared to solid-state parts such as Flash memory.

Hello,

We try to work with usb device controller with apollo lake e3900 (using congatec ma5).

My steps:

1. compile kernel 4.4.0 with dwc2 and dwc3 as modules, and build all controllers in device-drivers->usb->usb-> gadget->usb peripheral (build into kernel).

2. boot system

3.  modprobe libcomposite

    modprobe dwc2

     ls /sys/class/udc shows that it is empty !

    trying modprobe dwc3 gives same result.

As I understand usb device should be supported with E3900 "USB 2.0 interfaces on the COM Express connector including one USB 2.0 Dual Role port. "

Thank you for any idea,

ranran

Hi,

We are developing coreboot for Apollo lake custom board. We have enabled "MRC training data Saving" and "Enable FastBoot" in Fsp using BCT tool.

We have the FSP source (MR5).

After this we observed the boot time reduced from 31 sec to 23 sec for very first boot and 11sec for consequent boots.

We would like to reduce the boot time to the lowest as possible. We found the below logs which shows that the memory Initialization takes more time.

Coreboot FSP Performance Data

Coreboot FSP Performance Data

ID: 950 - 951: 8118676370 - 2354813461 --> 4433ms        ===============> Memory Initialization

ID: 952 - 953: 10675414728 - 8905813067 --> 1361ms

ID: 954 - 955: 11761158519 - 10934089420 --> 636ms

ID: 956 - 957: 19265617974 - 19265559282 --> 0ms

1. Could you please help us to reduce the memory initialization time ?
2. Can we extract the MRC data and preload it to reduce the boot time?

Thanks,

Antony

hello,

We have designed a ccustom board based on Minnowboard Max (using E3815 processor) and currently testing the board using Minnowboard Max bios.

On power up, processor starts reading the boot flash but after 100msec it stops reading the flash...... No data is being read on the PCU serial port also...

What is causing hanging of Flash memory read after 100 ms?

In this, the second of Curtiss-Wright's series of papers on the use of commercial-off-the-shelf (COTS) technologies to address Trusted Computing requirements, we take a look at Trusted Boot, a key strategy for ensuring that the trustworthiness of an embedded system begins with the very first software instruction at system startup in order to protect against attacks.

What does “trust” mean in an embedded module or system? Trust means no more and no less than ensuring that the system operates exactly as intended. In the context of the boot process, trust means that an embedded module only executes the boot code, operating system, and application code that it is intended to run. No more and no less. The only way to guarantee trust in this chain is to ensure that all code, from the very first instruction that a processor executes, is authentic. In other words, that the code is specifically intended by the OEM or system integrator to execute on that processor. This paper focuses particularly on establishing initial trust in the boot process and various means to do that, although many of these same techniques are also useful for extending trust to the operating system and application code.

Download the 'Trusted Boot' white paper to learn more about:

• Trusted Boot
• Cryptography
• Intel Trusted Execution Technology (TXT) and Boot Guard
• NXP Trust Architecture for Power Architecture and Arm processors

Read more White Papers in the Trusted Computing series

• An Introduction to COTS-based Trusted Computing White Paper
• Root of Trust: A Foundation for Trusted Computing
• TrustedCOTS - Leading the Way to Secure Systems

Hello,

I am looking for MIPI-CSI interface specifications or application note for Intel ATOM E3826, as very limited information is available on datasheet.

Does SoC supports Interlaced and progressive format for video capture?

I have atom-e3800-mipi-csi2-camera-sub-system-paper with me but it have limited information for the interface.

Hi

I have to temperature cycle the processor on a ceramic board between ideally +105 C and -55 C. I can make a case for limiting the higher temperature to 85C based on encapsulant but would like confirmation of storage temperature. I have the thermal design guide for the E3800 family but the guide deals with operating conditions. Any idea if the E3825 can survive 105C non-operating?

Thanks

Hello Intel,

I used i210 device off function, and look datasheet 6.2.19 bit15 setting to 1b.

So I change value B200 at address 0x1E.

And circuit used jumper JP_LAN2 setting pin.28

Then have two setting

1. 1-2 : Enable Lan i210

2. 2-3 : Disable Lan i210

Test jumper JP_LAN2, and setting 1-2 then power on.

It can see i210 operation under windows 10.

Test finish, shunt down windows.

I will setting 2-3 at JP_LAN2. => Power on => But still can see i210 operation under windows.

I need disable i210 after shunt down windows again.

What does mistake in circut or i210 code ?

Best regards,

Hi Everybody!

Our company develops a motherboard on the processor Intel atom c3538.

Mostly our motherboard used intel reference board design, but there are some changes that do not allow using the BIOS from the reference board.

We need build custom bios (bootloader, silicon initialization, etc.) for our motherboard.

1.    We need a download link to the COREBOOT source code file for Intel Atom® Processor C3538 (denverton ns) or for Intel harcuvar platform. The file name (most likely) looks like fsp_bootloader-coreboot-xxxxxxxx.tar.gz. Or we must use coreboot from github?

2.    We need a link to download manual containing instruction about compiling the COREBOOT for Intel Atom® Processor C3538. The manual should contain information about configuring of COREBOOT package before compiling (about the necessary settings of .config file for our processor (harcuvar platform)).

3.    We need a link to download manual containing instruction about integration procedure of Intel Firmware Support Package (FSP) binary into coreboot. After working with the «BCT-master» program, we got files with the extension *.rom. Where can we find instructions on how to integrate these files into the coreboot?

4.    We need a link to download latest CPU Microcode for Intel atom c3538 and manual about procedure of integration it into coreboot.

5.    We need a link to download Intel Flash Image Tool (FITC) tool for Intel Atom® Processor C3538.

I will be very grateful for any information about the development (modification) of the BIOS for our motherboard. What else is needed to development (modificate) single SPI flash image file for Intel Atom® Processor C3538 motherboard? (Trusted Execution Engine (TXE)?, Flash Descriptor.bin?, OEM Section.bin?, GbE Region.bin?, ME Region.bin?)

Is there an example of bulding a LKM (Loadable Kernel Module) for the DE10-Nano board?

Hi,

I am trying to activate the Ethernet Controller (WGI210IT)  with an external flash (MX25L1633EM2I). Currently the both controller's (internal flash) iNVM and the external flash are blank. Thus the controller is identified on a Linux ARM machine via PCIe as 1531 device ID. I got the 572162-eepromaccesstool-0-7-5.zip and run the EepromAccess Tool and tried to dump the iNVM to file but the application got stuch because it was waiting for the GetFlswFlashOperationDone to complete but it didn't as the read PCIe register returned 0xFFFF_FFFF. Moreover, I saw that the memory mapped is disables:

01:00.0 Ethernet controller: Intel Corporation Device 1531 (rev 03)

Subsystem: Intel Corporation Device 0000

Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-

Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Interrupt: pin A routed to IRQ 388

Region 0: Memory at 50800000 (32-bit, non-prefetchable) [disabled] [size=8M]

Region 2: I/O ports at 1000 [disabled] [size=32]

Region 3: Memory at 50400000 (32-bit, non-prefetchable) [disabled] [size=16K]

Capabilities: <access denied>

I guess this is why the register returns NA values. Moreover the igb driver does not support 1531 Device ID and thus it is not attached to the device. I read the forums and I understand that the external flash supposed to be programmed to enable the regions mapping to make the igb driver to be utilized with the i210 (which shall be identified with a different device ID).

I have the following questions:

1) I should I program the external flash?

2) Is there away to program the flash via the ARM processor?

Regards,

Igal.

Hi ,

I am trying to bring up a new Apollo Lake-based platform with a coreboot+SeaBIOS combination - it is very similar to the Leaf Hill CRB so I adapted my platform code using the Leaf Hill project as base. I stitched the coreboot outputs into an IFWI as instructed by the Apollo_Lake_Coreboot_MR1_Release_Notes.pdf. I ran the resulting output binary on an Leaf Hill CRB, and the binary runs successfully up until RAM initialization phase where it stops (due differences in board ID and RAM type, so this stop is expected, point being it looks like the binary works as expected).

However, when I try to run the binary on my brand new platform, which is programmed for the first time ever, then I can see using an oscilloscope that the binary's flash descriptor section is read (the first 332 bytes of the binary, as this is the length of the descriptor's content). Thereafter all SPI transactions stop. See below flash map:

Start (hex)    End (hex)    Length (hex)    Area Name

-----------    ---------    ------------    ---------

00000000       007FFFFF     00800000        Full Flash Image

00000014       00000017     00000004            FLMAP0 - Flash Map 0 Register

00000018       0000001B     00000004            FLMAP1 - Flash Map 1 Register

0000001C       0000001F     00000004            FLMAP2 - Flash Map 2 Register

00000030       0000003B     0000000C            FCBA - Flash Component Registers

00000040       00000043     00000004            FLREG0 - Flash Region 0 (Flash Descriptor) Register

00000044       00000047     00000004            FLREG1 - Flash Region 1 (IFWI) Register

00000048       0000004B     00000004            FLREG2 - Flash Region 2 (Intel(R) TXE) Register

00000050       00000053     00000004            FLREG4 - Flash Region 4 (Platform Data) Register

00000054       00000057     00000004            FLREG5 - Flash Region 5 (Device Expansion) Register

00000060       00000063     00000004            FLREG8 - Flash Region 8 (Embedded Controller) Register

00000080       00000083     00000004            FLMSTR1 - Flash Master 1 (Host CPU/BIOS)

00000084       00000087     00000004            FLMSTR2 - Flash Master 2 (Intel(R) TXE)

00000100       000002FF     00000200            FPSBA - SoC Straps (Including Padding)

00000DF0       00000EFF     00000110            VSCC Table

00000DF0       00000DF7     00000008                W25Q128FW

00000DF8       00000DFF     00000008                ATF26DF321

00000E00       00000E07     00000008                N25Q128

00000E08       00000E0F     00000008                N25Q064

00000E10       00000E17     00000008                MT25QU128ABA

00001000       0037FFFF     0037F000        Boot Partition 1

00001000       000F9FFF     000F9000            Primary Boot Partition

00001200       0000120F     00000010                IFP Overrides Partition

00001210       00001317     00000108                Unified Emulation Partition (UEP)

00002000       00004FFF     00003000                OEM SMIP Partition

00005000       0000EFFF     0000A000                CSE RBE Partition

0000F000       0001EFFF     00010000                PMCP

0001F000       0007AFFF     0005C000                CSE BUP Partition

0007B000       0007EFFF     00004000                uCode Partition

0007B040       0007EC3F     00003C00                    uCode Patch 1

0007F000       000F7FFF     00079000                IBB Partition

000F8000       000F9FFF     00002000                Debug Token Partition

000FA000       00200FFF     00107000            Secondary Boot Partition

000FA200       00200FFF     00106E00                CSE Main Partition

00380000       006FEFFF     0037F000        Boot Partition 2

00380000       003801FF     00000200            Primary Boot Partition

00380200       00481FFF     00101E00            Secondary Boot Partition

00381000       00481FFF     00101000                OBB Partition

006FF000       007FEFFF     00100000        TXE Data Region

I suspect this is because the TXE bypass ROM has not been programmed yet, but I do not know how to do this. I tried to simply program the "cse_image.bin" that accompanied the FIT tool I am using to stitch with, onto the flash device and then cycle power on the board, but during power-on SPI transactions stops right after the flash descriptor's signature (at address 0x10) is read. Then I reloaded my original IFWI binary and ran it, but there's no difference to previous attempts.

I also tried to enable the "Firmware ROM Bypass" setting in FIT tool but this option is grayed out in the FIT tool and cannot be selected - please see attached screen shot. (Also tried enabling it in the XML file used by FIT, and in a next attempt tried to manually set the corresponding bit in the final binary itself, but no success).

Please can you maybe point me to instructions that explain how to program brand new hardware for the first time after the hardware is produced? Or can you please maybe tell me what I am doing wrong? Do I need to strap any resistors for the bring-up (that differs from recommended operational strapping)? Been struggling for some time and have no idea how to go forward!

Best regards,

I did the following:

I made a new PCB layout copying the arduino 101 schematic and omitting the periperals (as BLE) of the Curie Module using C1000 instead.

Due to the fact that there is no exact schematic of the Curie Module I guessed the wireing from the C1000 development platform.

I uploaded an arduino 101 bootloader via JTAG interface into the C1000.

As a result the board is recognized by the Arduino IDE (1.8.5, versions.txt) , both Windows drivers are loaded , I can fetch the serial number of the board via the USB/COM port and I can upload sketches without error messages (compileMsg.txt).

Unfortunately the sketches do not run. Even a simple blinky-sketch (blinky.ino) does not work.

Does the code check for the presence of the bluetooth chip or other peripherals and hangs, if no response is received?

I would appreciate to get your ideas on this.

Thanks in advance.

Hi,

We would like to build coreboot image for Apollo lake platform. We are using

• Coreboot-4.8.1
• Apollo lake Intel FSP_2_0

We have built the coreboot source and created coreboot.rom image with the below warning message:

** WARNING **

coreboot will be built without an Intel Firmware Descriptor.

Never write a complete coreboot.rom without an IFD to your

board's flash chip! You can use flashrom's IFD or layout

parameters to flash only to the BIOS region.

Is the coreboot.rom image is enough to flash ? Could you please provide feedback on this ?

Could you please share "Apollo_Lake_Coreboot_MR5_Release_Notes.pdf" ?

Thanks,

Antony

Hi, I hope I'm posting in the correct place.

I installed Quartus II 13.1 on my Linux Mint Sylvia 18.3. I made sure to install the 32-bit dependencies that I found listed on this site:

Matthew's Mumblings: Making ModelSim ALTERA STARTER EDITION vsim 10.1d work on Ubuntu 14.04

I noticed no error messages during or after install. But when I try to open Quartus, I get the following:

First off, when it asked to Retrieve the Web License it won't connect. I had read that these web versions that need a license.

Secondly, this error message, beyond which I cannot proceed

*** Fatal Error: Segment Violation at (nil)

Module: quartus

Stack Trace:

  0x85ce3: lh_insert + 0xb3 (tls1.6)

  0x7a48c: OBJ_NAME_add + 0x6c (tls1.6)

  0x4bba8: SSL_library_init + 0x38 (ssl.so.1.0.0)

  0x1a0056: QObject::event(QEvent*) + 0x376 (QtCore.so.4)

  0x1fd924: QApplicationPrivate::notify_helper(QObject*, QEvent*) + 0xb4 (QtGui.so.4)

  0x2024df: QApplication::notify(QObject*, QEvent*) + 0x12f (QtGui.so.4)

  0x18b27c: QCoreApplication::notifyInternal(QObject*, QEvent*) + 0x8c (QtCore.so.4)

  0x18e8a8: QCoreApplicationPrivate::sendPostedEvents(QObject*, int, QThreadData*) + 0x328 (QtCore.so.4)

  0x18a062: QEventLoop::processEvents(QFlags<QEventLoop::ProcessEventsFlag>) + 0x32 (QtCore.so.4)

  0x18a31d: QEventLoop::exec(QFlags<QEventLoop::ProcessEventsFlag>) + 0x14d (QtCore.so.4)

  0x18ed4b: QCoreApplication::exec() + 0xbb (QtCore.so.4)

  0x7dc1: __gxx_personality_v0 + 0x3b9 (quartus)

  0x3bb9a: msg_main_thread(void*) + 0x10 (ccl_msg)

  0x75bc: thr_final_wrapper + 0xc (ccl_thr)

  0x3c801: msg_thread_wrapper(void* (*)(void*), void*) + 0x5b (ccl_msg)

  0x16e45: mem_thread_wrapper(void* (*)(void*), void*) + 0xc5 (quartus)

  0xf41d: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)

  0x799c: thr_thread_wrapper + 0x15 (ccl_thr)

  0x4e41d: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0x96 (ccl_msg)

  0x7e85: __gxx_personality_v0 + 0x47d (quartus)

  0x20830: __libc_start_main + 0xf0 (c.so.6)

  0x7c99: __gxx_personality_v0 + 0x291 (quartus)

End-trace

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version

Can anyone suggest the right course of action to get Quartus II working on my work-station?

Thank you

Hi,

I read document '571613_IntelAtom_E3900_ApolloLake_I_Android_ReleaseNotes_Rev1_6.pdf' and follow this guide.

I build android Marshmallow  successful and boot on Leaf Hill CRB.

It show warning message : " BOOT_STATE is RED but allow to boot anyway on eng builds! "

I want to handle message and cancel warning.

How can I do?

If I want to build user mode, how can I set it up?

Thanks.

Hi all,

I was sent here from this thread to ask my question again:

I wonder if Intel consider releasing Atom C3000 (Denverton) Firmware Support Package, so independent developers can create firmware for their own platforms.

If yes then what is the roadmap for that ? If no, then what is the reason ?

Best Regards,

Hi.

I am currently working on a coreboot/U-Boot based custom boot solution. At the moment the used COM express board works most of the time. If it fails it looks like there are some global resets triggered by the FSP followed by wired pcie resets which can result in a total hang or in boot times more then one minute.

Some coreboot guys told me that I should try to get access to a debug version of the FSP. I really need to get this working asap and the next Apollo Lake based design is waiting for me (if the FSP/coreboot/U-Boot plan works).

I think my employer should have the nessesary NDA with Intel.